No. During T3 of M1 the first byte of an instruction is sent over the internal data bus to the instruction register IR, while most instructions that use T3 in M2, M3, or later, also use the data bus in some way. E.g., LD r,(HL) (MOV r,M in 8080 mnemonics, also see item 2 in Figure 2.27) puts the data received from the memory location "(HL)" into the general-purpose register "r" using the data bus.
2.5 Mhz, is the same as 400 ns/cycle. The instruction is 9 clock cycles long, but the last 2 cycle overlap with the first 2 cycles of the next instruction. The resulting 7 clock cycles of 400 ns each result in an apparent execution time of 2.8 us.
The contents of PC (not WZ) is pushed to stack, and when returning from the interrupt, the PC would be loaded with the old value from stack. Effectively, the JP would be cancelled.