This chapter will first analyze the various classes of instructions which should be available in a general-purpose computer. It will then analyze one by one all of the instructions available for the Z80, and explain in detail their purpose and the manner in which they affect flags or can be used in conjunction with various addressing modes. A detailed discussion of addressing techniques will be presented in Chapter 5.
Instructions may be classified in many ways, and there is no standard. We will distinguish five main categories of instructions:
Data transfer instructions will transfer data between registers, or between a register and memory, or between a register and an input/output device. Specialized transfer instructions may exist for registers which play a specific role. For example, push and pop operations are provided for efficient stack operation. They will move a word of data between the top of the stack and the accumulator in a single instruction, while automatically updating the stack pointer register.
Data processing instructions fall into five general categories:
It should be noted that, for efficient data processing, it is desirable to have powerful arithmetic instructions, such as multiply and divide. Unfortunately, they are not available on most microprocessors. It is also desirable to have powerful shift and skew instructions, such as shift n bits, or a nibble exchange, where the right half and the left half of the byte are exchanged. These are also usually unavailable on most microprocessors.
Before examining the actual Z80 instructions, let us recall the difference between a shift and a rotation. The shift will move the contents of a register or a memory location by one bit location to the left or to the right. The bit falling out of the register will go into the carry bit. The bit coming into the other side will be a "0" except in the case of an "arithmetic shift right," where the MSB will be duplicated.
In the case of a rotation, the bit coming out still goes into the carry. However, the bit coming in is the previous value which was in the carry bit. This corresponds to a 9-bit rotation. It is often desirable to have a true 8-bit rotation where the bit coming in on one side is the one falling from the other side. This is not provided on most microprocessors but is available on the Z80 (see Figure 4.1).
Finally, when shifting a word to the right, it is convenient to have one more type of shift, called a sign extension or an "arithmetic shift right." When doing operations on two's complement numbers, particularly when implementing floating-point routines, it is often necessary to shift a negative number to the right. When shifting a two's complement number to the right, the bit which must come in on the left side should be a "1" (the sign should get repeated as many times as needed by successive shifts). This is the arithmetic shift right.
Fig. 4.1: Shift and Rotate
The test instruction will test bits in the specified register for "0" or "1", or combinations. At a minimum, it must be possible to test the flags register. It is, therefore, desirable to have as many flags as possible in this register. In addition, it is convenient to be able to test for combinations of such bits with a single instruction. Finally, it is desirable to be able to test any bit position in any register, and to test the value of a register compared to the value of any other register (greater than, less than, equal). Microprocessor test instructions are usually limited to testing single bits of the flags register. The Z80, however, offers better facilities than most.
The jump instructions that may be available generally fall into three categories:
It is convenient to have two- or even three-way jumps, depending, for example, on whether the result of a comparison is "greater than," "less than," or "equal." It is also convenient to have skip operations, which will jump forward or backward by a few instructions. However, a "skip" is equivalent to a "jump." Finally, in most loops, there is usually a decrement or increment operation at the end, followed by a test-and-branch. The availability of a single-instruction increment/decrement plus test-and-branch is, therefore, a significant advantage for efficient loop implementation. This is not available in most microprocessors. Only simple branches, combined with simple tests, are available. This, naturally, complicates programming and reduces efficiency. In the case of the Z80, a "decrement and jump" instruction is available. However, it only tests a specific register (B) for zero.
Input/output instructions are specialized instructions for the handling of input/output devices. In practice, a majority of the 8-bit microprocessors use memory-mapped I/O: input/output devices are connected to the address bus just like memory chips, and addressed as such. They appear to the programmer as memory locations. All memory-type operations normally require 3 bytes and are, therefore, slow. For efficient input/output handling in such an environment, it is desirable to have a short addressing mechanism available so that I/O devices whose handling speed is crucial may reside in page 0. However, if page 0 addressing is available, it is usually used for RAM memory, which prevents its effective use for input/output devices. The Z80, like the 8080, is equipped with specialized I/O instructions. As a result, in the case of the Z80, the designer may use either method: input/output devices may be addressed as memory devices, or else as input/output devices, using the I/O instructions.
They will be described later in this chapter.
Control instructions supply synchronization signals and may suspend or interrupt a program. They can also function as a break or a similated interrupt. (Interrupts will be described in Chapter 6 on Input/Output Techniques.)
The Z80 microprocessor was designed to be a replacement for the 8080, and to offer additional capabilities. As a result of this design philosophy, the Z80 offers all the instructions of the 8080, plus additional instructions. In view of the limited number of bit available in an 8-bit opcode, one may wonder how the designers of the Z80 succeeded in implementing many additional ones. They did so by using a few unused 8080 opcodes and by adding an additional byte to the opcode for indexed operations. This is why some of the Z80 instructions occupy up to five bytes in the memory.
It is important to remember that any program can be written in many different ways. A thorough knowledge and understanding of the instruction set is indispensable for achieving efficient programming. However, when learning how to program, it is not essential to write optimized programs. During a first reading of this chapter, it is therefore unimportant to remember all the various instructions. It is important to remember the categories of instructions and to study typical examples. Then, when writing programs, the reader should consult the Z80 instruction set description, and select the instructions best suited to his needs. The various instructions of the Z80 will therefore be reviewed in logical categories. The reader interested in exploring the capabilities of the various instructions is referred to the individual descriptions of the instructions.
We will now examine the capabilities provided by the Z80 in terms of the five classes of instructions which have been defined at the beginning of this chapter.
Data transfer instructions on the Z80 may be classified in four categories: 8-bit transfers, 16-bit transfers, stack operations, and block transfers. Let us examine them.
All eight-bit data transfers are accomplished by load instructions. The format is:
LD destination, source
For example, the accumulator A may be loaded from register B by using the instruction:
LD A,B
Direct transfers may be accomplished between any two of hte working registers (ABCDEHL).
In order to load any of the working registers, except for the accumulator, from a memory location, the address of this memory location must first be loaded into the H-L register pair.
For example, in order to load register C from memory location 1234, register H and L will first have to be loaded with the value "1234". (A load instruction operating on 16 bits will be used. This is described in the following section.)
Then, the instruction LD C,(HL) will be used and will accomplish the desired result.
The accumulator is an exception. It can be loaded directly from any specified memory location. This is called the extended addressing mode. For example, in order to load the accumulator with the contents of memory location 1234, the following instruction will be used:
LD A,(1234H) |
(Note the use of the "( )" to denote "contents of.") |
| address | PC | : 3A | (opcode) |
| PC + 1 | : 34 | (low order half of the address) | |
| PC + 2 | : 12 | (high order half of the address) |
Note that the address is stored in "reverse order" in the instruction itself:
| 3A | low addr | high addr |
All the working registers may also be loaded with any specified eight-bit value, or "literal," contained in the second byte of the instruction (this is called immediate addressing). An example is:
LD E,12H
which loads register E with the value 12 hexadecimal.
In the memory, the instruction appears as:
| address | PC | : 1E | (opcode) |
| PC + 1 | : 12 | (literal operand) |
As a result of this instruction, the immediate operand, or literal value will be contained in register E.
The indexed addressing mode is also available for loading register contents, and will be fully described in the next chapter on addressing techniques. Other miscellaneous possibilities exist for loading specific registers, and a table listing all the possibilities is shown in Figure 4.2 (tables supplied by Zilog, Inc.). The grey areas show instructions common with the 8080A.
Fig. 4.2: Eight-Bit Load Group - 'LD'
Basically, any of the 16-bit register pairs, BC, DE, HL, SP, IX, IY, may be loaded with a literal 16-bit operand, or from a specified memory address (extended addressing), or from the top of the stack, i.e., from the address contained in SP. Conversely, the contents of these register pairs may be stored in the same manner at a specified memory address or on top of the stack. Additionally, the SP register may be loaded from HL, IX, and IY. This facilitates creating multiple stacks. The register pair AF may also be pushed on top of the stack.
The table listing all the possibilities is shown in Figure 4.3. The stack push and pop operations are included as parts of the 16-bit data transfers. All stack operations transfer the contents of a register pair to or from the stack. Note that there are no single push and pop instructions for saving individual eight-bit registers.
Fig. 4.3: 16-Bit Load Group - 'LD', 'PUSH' and 'POP'
A double-byte push or pop is always executed on a register pair: AF, BC, DE, HL, IX, IY (see the bottom row and the right-most column in Figure 4.3).
When operating on AF, BC, DE, HL, a single-byte is required for the instruction, resulting in good efficiency. For example, assume that the stack pointer SP contains the value "0100". The following instruction is executed:
PUSH AF
When pushing the contents of the register pair on the stack, the stack pointer SP is first decremented, then the contents of register A are deposited on top of the stack. Then the SP is decremented again, and the contents of F are deposited on the stack. At the end of the stack transfer, SP points to the top element of the stack, which in our example is the value of F.
It is important to remember that, in the case of the Z80, the SP points to the top of the stack and the SP is decremented whenever a register pair is pushed. Other conventions are often used in other processors, and this may be a source of confusion.
Additionally, a specialized mnemonic EX has been reserved for exchange operations. EX is not a simple data transfer, but a dual data transfer. It actually changes the contents of two specified locations. EX may be used to exchange the top of the stack with HL, IX, IY and also to swap the contents of DE and HL, and AF and AF' (remember that AF' stands for the other AF register pair available in the Z80).
Finally, a special EXX instruction is available to exchange the contents of BC, DE, HL with the contents of the corresponding registers in the second register bank of the Z80.
The possible exchanges are summarized in Figure 4.4.
Fig. 4.4: Exchanges 'EX' and 'EXX'
Block transfer instructions are instructions which will result in the transfer of a block of data rather than a single or double byte. Block transfer instructions are more complex for the manufacturer to implement than most instructions and are usually not provided on microprocessors. They are convenient for programming, and may improve the performance of a program, especially during input/output operations. Their use and advantages will be demonstrated throughout this book. Some automatic block transfer instructions are available in the case of the Z80. They use specific conventions.
All block transfer instructions require te use of three pairs of registers: BC, DE, HL:
| BC is used as a 16-bit counter. This means that uup to 216 = 64K bytes may be moved automatically. HL is used as the source pointer. It may point anywhere in the memory. DE is used as the destination pointer and may point anywhere in the memory. |
Four block transfer instructions are provided:
LDD, LDDR, LDI, LDIR
All of them decrement the counter BC with each transfer. Two of them decrement the pointer registers DE and HL, LDD and LDDR, while the two others increment DE and HL, LDI and LDIR. For each of these two groups of instructions, the letter R at the end of the mnemonic indicates an automatic repeat. Let us examine these instructions.
LDI stands for "load and increment." It transfers one byte from the memory location pointed to by H and L to the destination in the memory pointed to by D and E. It also decrements BC. It will automatically increment H and L and D and E so that all register pairs are properly conditioned to perform the next byte transfer whenever required.
LDIR stands for "load, increment and repeat," i.e., execute LDI repeatedly until the counter registers BC reach the value "0". It is used to move a continuous block of data automatically from one memory area to another.
LDD and LDDR operate in the same way except that the address pointers are decremented rather than incremented. The transfer therefore starts at the highest address in the block instead of the lowest. The effect of the four instructions is summarized in Figure 4.5.
Fig. 4.5: Block Transfer Group
Similar automated instructions are available for CP (compare) and are summarized in Figure 4.6.
Fig. 4.6: Block Search Group
Two main arithmetic operations are provided: addition and subtraction. They have been used extensively in the previous chapter. There are two types of addition, with and without carry, ADC and ADD respectively. Similarly, two types of subtractions are provided, with and without carry. They are SBC and SUB.
Additionally, three special instructions are provided: DAA, CPL, and NEG. The Decimal Adjust Accumulator instruction DAA has been used to implement BCD operations. It is normally used for each BCD add or subtract. Two complementation instructions are available. CPL will compute the one's complement of the accumulator, and NEG will negate the accumulator into its complement format (two's complement).
All the previous instructions operate on eight-bit data. 16-bit operations are more restricted. ADD, ADC, and SBC are available on specific registers, as described in Figure 4.8.
Finally, increment and decrement instructions are available which operate on all registers, both in an eight-bit and a 16-bit format. They are listed in Figure 4.7 (eight-bit operations) and 4.8 (16-bit operations).
Fig. 4.7: Eight-Bit Arithmetic and Logic
Note that, in general, all artithmetic operations modify some of the flags. Their effect is fully described in the instruction descriptions later in this chapter. However, it is important to note that INC and DEC instructions which operate on register pairs do not modify any of the flags. This detail is important to keep in mind. This means that if you increment or decrement on the of the register pairs to the value "0", the Z-bit in the flags register will not be set. The value of the register must be explicitly tested for the value "0" in the program.
Also, it is important to remember that the instructions ADC and SBC always affect all the flags. This does not mean that all the flags will necessarily be different after their execution. However, they might.
Fig. 4.8: Sixteen-Bit Arithmetic and Logic
Three logical operations are provided: AND, OR (inclusive) and XOR (exclusive), plus a comparison instruction CP. They all operate exclusively on eight-bit data. Let us examine them in turn. (A table listing all the possibilities and operation codes for these instructions is part of Figure 4.7.)
Each logical operation is characterized by a truth table, which expresses the logical value of the result in function of the inputs. The truth table for AND appears below:
| 0 AND 0 = 0 0 AND 1 = 0 1 AND 0 = 0 1 AND 1 = 1 |
or |
|
The AND operation is characterized by the fact that the output is quot;1" only if both inputs are "1". In other words, if one of the input is "0", it is guaranteed that the result is "0". This feature is used to zero a bit position in a word. This is called "masking."
One of the important uses of the AND instruction is to clear or "mask out" one or more specified bit positions in a word. Assume for example that we want to zero the right-most four-bit positions in a word. This will be performed by the following program:
LD A,WORD WORD CONTAINS '10101010' AND 11110000B '11110000' IS MASK
Let us assume that WORD is equal to '10101010'. The result of the program is to leave the value '10100000' in the accumlator. "B" is used to indicate a binary value.
| Exercise 4.1: | Write a three-line program which will zero bits 1 and 6 of WORD. |
| Exercise 4.2: | What happens with a MASK = '11111111'? |
This instruction is the inclusive OR operation. It is characterized by the following truth table:
| 0 OR 0 = 0 0 OR 1 = 1 1 OR 0 = 1 1 OR 1 = 1 |
or |
|
The logical OR is characterized by the fact that if one of the operands is "1", then the result is always "1". The obvious use of OR is to set any bit in a word to "1".
Let us set the right-most four bits of WORD to 1's. The program is:
LD A,WORD OR 00001111B
Let us assume that WORD did contain '10101010'. The final value of the accumulator will be '10101111'.
| Exercise 4.3: | What would happen if we were to use the instruction OR 10101111B? |
| Exercise 4.4: | What is the effect of ORing with "FF" hexadecimal? |
XOR stands for "exclusive OR." The exclusive OR differs from the inclusive OR that we have just described in one respect: the result is "1" only if one, and only one, of the operands is equal to "1". If both operands are equal to"1", the normal OR would give a "1" result. The exclusive OR gives a "0" result. The truth table is:
| 0 XOR 0 = 0 0 XOR 1 = 1 1 XOR 0 = 1 1 XOR 1 = 0 |
or |
|
The exclusive OR is used for comparisons. If any bit is different, the exclusive OR of two words will be non-zero. In addition, in the case of the Z80, the exclusive OR may be used to complement a word, since there is no complement instruction on anything but the accumulator. This is done by performing the XOR of a word with all ones. The program appears below:
LD A,WORD XOR 11111111B
Let us assume the WORD contained "10101010". The final value of the register will be "01010101". You can verify that it is the complement of the original value.
XOR can be used to advantage as a "bit toggle."
| Exercise 4.5: | What is the effect of XOR using a register with "00" hexadecimal? |
Let us first differentiate between the shift and the rotate operations, which are illustrated in Figure 4.9. In a shift operation, the contents of the register are shifted to the left or to the right by one bit position. The bit which falls out of the register goes into the carry bit C, and the bit which comes in is zero. This was explained in the previous section.
Fig. 4.9: Shift and Rotate
One exception exists: it is the shift-right-arithmetic. When performing operations on negative numbers in the two's complement format, the left-most bit is the sign bit. In the case of negative numbers it is "1". When dividing a negative number by "2" by shifting it to the right, it should remain negative, i.e., the left-most bit should remain "1". This is performed automatically by the SRA instruction or Shift Right Arithmetic. In this arithmetic shift right, the bit which comes in on the left is identical to the sign bit. It is "0" if the left-most bit was a "0", and "1" if the left-most bit was a "1". This is illustrated on the right of Figure 4.10, which shows all the possible shift and rotate operations.
Fig. 4.10: Rotates and Shifts
A rotation differs from a shift by the fact that the bit coming into the register is the one which will fall from either the other end of the register or the carry bit. Two types of rotations are supplied in the case of the Z80: an eight-bit rotation and a nine-bit rotation.
The nine-bit rotation is illustrated in Figure 4.11. For example, in the case of a right rotation, the eight bits of the register are shifted right by one bit position. The bit which falls off the right part of the register goes, as usual, into the carry bit. At the same time the bit which comes in on the left end of the register is the previous value of the carry bit (before it is overwritten with the bit falling out). In mathematics this is called a nine-bit rotation since the eight bits of the register plus the ninth (the carry bit) are rotated to the right by one bit position. Conversely, the left rotation accomplishes the same result in the opposite direction.
Fig. 4.11: Nine-Bit Rotation
The eight-bit rotation operate in a similar way. Bit 0 is copied into bit seven, or else bit seven is copied into bit 0, depending on the direction of the rotation. In addition, the bit coming out of the register is also copied in the carry bit. This is illustrated by Figure 4.12.
Fig. 4.12: Eight-Bit Rotation
Two special digit-rotate instructions are provided to facilitate BCD arithmetic. The result is a four-bit rotation between two digits contained in the memory location pointed to by the HL registers and the digit in the lower half of the accumulator. This is illustrated by Figure 4.13.
Fig. 4.13: Digit Rotate Instruction (Rotate Decimal)
It has been shown above how the logical operations may be used to set or reset bits or groups of bits in the accumulator. However, it is convenient to set or reset any bit in any register or memory location with a single instruction. This facility requires a considerable number of opcode and is therefore usually not provided on most microprocessors. However, the Z80 is equipped with extensive bit-manipulation facilities. They are shown in Figure 4.14. This table also includes the test instructions which will be described only in the next section.
Fig. 4.14: Bit Manipulation Group
Two special instructions are also available for operating on the carry flag. They are CCF (Complement Carry Flag) and SCF (Set Carry Flag). They are shown in Figure 4.15.
Fig. 4.15: General-Purpose AF Operations
Since testing operations rely heavily on the use of the flags register, we will here describe in detail the role of each of the flags. The contents of the flags register appear in Figure 4.16.
Fig. 4.16: The Flags Register
C is the carry, N is add or subtract, P/V is parity or overflag, H is half carry, Z is zero, S is sign. Bits 3 and 5 of the flags register are not used ("-"). The two flags H and N are used for BCD arithmetic and cannot be tested. The other four flags (C, P/V, Z, S) can be tested in conjunction with conditional jump or call instructions.
The role of each flag will now be described.