Chapter 2 - Full TOC

Sections

2. Z80 HARDWARE ORGANIZATION 2.1 INTRODUCTION 2.2 SYSTEM ARCHITECTURE 2.3 INSIDE A MICROPROCESSOR 2.3.1 Setting Flags 2.3.2 The Registers 2.3.3 The General-Purpose Registers 2.3.4 The Address Registers 2.3.4.1 Program Counter (PC) 2.3.4.2 Stack Pointer (SP)

2.3.4.3 Index Register (IX) 2.3.5 The Stack 2.3.6 The Instruction Execution Cycle 2.3.6.1 Fetch 2.3.6.2 Decoding and Execution 2.3.7 Fetching the Next Instruction 2.3.8 The Critical Race Problem 2.4 INTERNAL ORGANIZATION OF THE Z80 2.5 INSTRUCTION FORMATS 2.5.1 A One-Word Instruction

2.5.2 A Two-Word Instruction 2.5.3 A Three-Word Instruction 2.6 EXECUTION OF INSTRUCTIONS WITHIN THE Z80 2.6.1 The FETCH Phase 2.6.2 The DECODE and EXECUTE Phases 2.6.2.1 Important Exercise: 2.6.3 The Z80 Chip 2.6.4 Internal Status and Sequencing 2.6.4 Memory and I/O Control 2.7 HARDWARE SUMMARY

Exercises

Exercise 2.1, Question 2.1, Question 2.2, Question 2.3

List of Figures

Fig. 2.1: Standard Z80 System Fig. 2.2: "Standard" Microprocessor Architecture Fig. 2.3: Shift and Rotate Fig. 2.4: The 16-bit Address Registers Create the Address Bus Fig. 2.5: The Two-Stack Manipulation Instructions Fig. 2.6: Fetching an Instruction from the Memory Fig. 2.7: Automatic Sequencing Fig. 2.8: Single-Bus Architecture Fig. 2.9: Execution of an Addition - R0 into ACC Fig. 2.10: Addition - Second Register R1 into ALU Fig. 2.11: Result Is Generated and Goes into R0 Fig. 2.12: The Critical Race Problem Fig. 2.13: Two Buffers Are Required (Temp Registers) Fig. 2.14: Internal Z80 Organization Fig. 2.15: Typical Instruction Formats Fig. 2.16: The Code Registers Fig. 2.17: Instruction Fetch - (PC) Is Sent to the Memory

Fig. 2.18: PC Is Incremented Fig. 2.19: The Instruction Arrives from the Memory into IR Fig. 2.20: Transferring C into D Fig. 2.21: The Contents of C Are Deposited into TMP Fig. 2.22: The Contents of TMP are Deposited into D Fig. 2.23: Two Transfers Occur Simultaneously Fig. 2.24: End of ADD r Fig. 2.25: FETCH-EXECUTE Overlap during T1-T2 Fig. 2.26: Intel Abbreviations Fig. 2.27: Intel Instruction Formats Fig. 2.28: Transfer Contents of HL to Address Bus Fig. 2.29: LD A,(ADDRESS) Is a 3-Word Instruction Fig. 2.30: Before Execution of LD A Fig. 2.31: After Execution of LD A Fig. 2.32: Second Byte of Instruction Goes into Z Fig. 2.33: Z80 MPU Pin out