SRA s

Shift right arithmetic s.
Function:
 
Format: s: may be r, n, (HL), (IX + d), or (IY + d)
 
r  
 
1100 1011
 
byte 1: CB
 
0010 1rrr
 
byte 2
 
(HL)  
 
1100 1011
 
byte 1: CB
 
0010 1110
 
byte 2: 2E
 
(IX + d)  
 
1101 1101
 
byte 1: DD
 
1100 1011
 
byte 2: CB
 
dddd dddd
 
byte 3: offset data
 
0010 1110
 
byte 4: 2E
 
(IY + d)  
 
1111 1101
 
byte 1: FD
 
1100 1011
 
byte 2: CB
 
dddd dddd
 
byte 3: offset data
 
0010 1110
 
byte 4: 2E
 
r may be any one of:
A
111
B
000
C
001
D
010
E
011
H
100
L
101
Description: The contents of the location determined by the specific operand are arithmetically shifted right. The contents of bit 0 being moved to the carry flag and the contents of bit 7 remain unchanged. The final result is stored back in the original location. s is defined in the descriptions of the similar RLC instructions.
 
Data Flow:
 
Timing:
s: M cycles: T states: usec
@ 2 MHz:
r
(HL)
(IX + d)
(IY + d)
2
4
6
6
8
15
23
23
4
7.5
11.5
11.5
 
Addressing Mode: r: implicit; (HL): indirect; (IX + d), (IY+d): indexed.
 
Byte Codes:
SRA  r
r:ABCDEHL
CB +2F28292A2B2C2D
 
Flags:
 
Example:
SRA  A

OBJECT CODE
Before:
 
After: