SRA s |
Shift right arithmetic s. |
Function: |
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Format: |
s: may be r, n, (HL), (IX + d), or (IY + d) |
r |
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byte 1: CB |
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byte 2 |
(HL) |
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byte 1: CB |
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byte 2: 2E |
(IX + d) |
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byte 1: DD |
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byte 2: CB |
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byte 3: offset data |
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byte 4: 2E |
(IY + d) |
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byte 1: FD |
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byte 2: CB |
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byte 3: offset data |
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byte 4: 2E |
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r may be any one of:
- A
- 111
- B
- 000
- C
- 001
- D
- 010
- E
- 011
- H
- 100
- L
- 101
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Description: |
The contents of the location determined by the specific operand are arithmetically shifted right. The contents of bit 0 being moved to the carry flag and the contents of bit 7 remain unchanged. The final result is stored back in the original location. s is defined in the descriptions of the similar RLC instructions. |
Data Flow: |
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Timing: |
s: |
M cycles: |
T states: |
usec @ 2 MHz: |
r
(HL)
(IX + d)
(IY + d) |
2
4
6
6 |
8
15
23
23 |
4
7.5
11.5
11.5 |
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Addressing Mode: |
r: implicit; (HL): indirect; (IX + d), (IY+d): indexed. |
Byte Codes: |
SRA r
r: | A | B | C | D | E | H | L |
CB + | 2F | 28 | 29 | 2A | 2B | 2C | 2D |
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Flags: |
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Example: |
SRA A |
OBJECT CODE |
Before: |
After: |
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