SRL s |
Logical shift right s. |
| Function: |
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| Format: |
s: may be r, n, (HL), (IX + d), or (IY + d)
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r
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byte 1: CB
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byte 2
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(HL)
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byte 1: CB
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byte 2: 3E
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(IX + d)
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byte 1: DD
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byte 2: CB
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byte 3: offset data
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byte 4: 3E
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(IY + d)
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byte 1: FD
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byte 2: CB
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byte 3: offset data
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byte 4: 3E
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r may be any one of:
- A
- 111
- B
- 000
- C
- 001
- D
- 010
- E
- 011
- H
- 100
- L
- 101
|
| Description: |
The contents of the location determined by the specific operand are logically shifted right. A zero is moved into bit 7 and the contents of bit 0 are moved into the carry flag. The final result is stored back in the original location.
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| Data Flow: |
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| Timing: |
| s: |
M cycles: |
T states: |
usec
@ 2 MHz: |
r
(HL)
(IX + d)
(IY + d) |
2
4
6
6 |
8
15
23
23 |
4
7.5
11.5
11.5 |
|
| Addressing Mode: |
r: implicit; (HL): indirect; (IX + d), (IY+d): indexed.
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| Byte Codes: |
SRL r
| r: | A | B | C | D | E | H | L |
|---|
| CB + | 3F | 38 | 39 | 3A | 3B | 3C | 3D |
|---|
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| Flags: |
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| Example: |
SRL E |
OBJECT CODE |
Before:
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After:
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