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SRL s

Logical shift right s.
Function:
 
Format: s: may be r, n, (HL), (IX + d), or (IY + d)
 
r  
 
1100 1011
 
byte 1: CB
 
0011 1rrr
 
byte 2
 
(HL)  
 
1100 1011
 
byte 1: CB
 
0011 1110
 
byte 2: 3E
 
(IX + d)  
 
1101 1101
 
byte 1: DD
 
1100 1011
 
byte 2: CB
 
dddd dddd
 
byte 3: offset data
 
0011 1110
 
byte 4: 3E
 
(IY + d)  
 
1111 1101
 
byte 1: FD
 
1100 1011
 
byte 2: CB
 
dddd dddd
 
byte 3: offset data
 
0011 1110
 
byte 4: 3E
 
r may be any one of:
A
111
B
000
C
001
D
010
E
011
H
100
L
101
Description: The contents of the location determined by the specific operand are logically shifted right. A zero is moved into bit 7 and the contents of bit 0 are moved into the carry flag. The final result is stored back in the original location.
 
Data Flow:
 
Timing:
s: M cycles: T states: usec
@ 2 MHz:
r
(HL)
(IX + d)
(IY + d)
2
4
6
6
8
15
23
23
4
7.5
11.5
11.5
 
Addressing Mode: r: implicit; (HL): indirect; (IX + d), (IY+d): indexed.
 
Byte Codes:
SRL  r
r:ABCDEHL
CB +3F38393A3B3C3D
 
Flags:
 
Example:
SRL  E

OBJECT CODE
Before:
 
After: