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Chapter 4 - Full TOC

Sections

4. THE Z80 INSTRUCTION SET
4.1 INTRODUCTION
4.2 CLASSES OF INSTRUCTIONS
4.2.1 Data Transfers
4.2.2 Data Processing
4.2.3 Test and Jump
4.2.4 Input/Output
4.2.5 Control Instructions
4.3 THE Z80 INSTRUCTION SET
4.3.1 Introduction
4.3.2 Data Transfer Instructions
4.3.2.1 Eight-Bit Data Transfers
4.3.2.2 16-Bit Data Transfers
4.3.3 Exchange Instructions
4.3.4 Block Transfer Instructions
4.3.5 Data Processing Instructions
4.3.5.1 Arithmetic
4.3.5.2 Logical

4.3.5.2.1 AND
4.3.5.2.2 OR
4.3.5.2.3 XOR
4.3.5.3 Skew Operations (Shift and Rotate)
4.3.5.3.1 Rotations
4.3.5.3.2 Special Digit Instructions
4.3.5.4 Bit Manipulation
4.3.6 Test and Jump
4.3.6.1 Carry (C)
4.3.6.2 Subtract (N)
4.3.6.3 Parity/Overflow (P/V)
4.3.6.4 The Half-Carry Flag (H)
4.3.6.5 Zero (Z)
4.3.6.6 Sign (S)
4.3.6.7 Summary of the Flags
4.3.7 The Jump Instruction
4.3.8 Input/Output Instructions
4.4 SUMMARY

Instructions

Abbreviations Used in the Descriptions
 
ADC A,s
ADC HL,ss
ADD A,(HL)
ADD A,(IX + d)
ADD A,(IY + d)
ADD A,n
ADD A,r
ADD HL,ss
ADD IX,rr
ADD IY,rr
AND s
BIT b,(HL)
BIT b,(IX + d)
BIT b,(IY + d)
BIT b,r
CALL cc,pq
CALL pq
CCF
CP s
CPD
CPDR
CPI
CPIR
CPL

DAA
DEC m
DEC rr
DEC IX
DEC IY
DI
DJNZ e
EI
EX AF,AF'
EX DE,HL
EX (SP),HL
EX (SP),IX
EX (SP),IY
EXX
HALT
IM 0
IM 1
IM 2
IN r,(C)
IN A,(N)
INC r
INC rr
INC (HL)
INC (IX + d)

INC (IY + d)
INC IX
INC IY
IND
INDR
INI
INIR
JP cc,pq
JP pq
JP (HL)
JP (IX)
JP (IY)
JR cc,e
JR e
LD dd,(nn)
LD dd,nn
LD r,n
LD r,r'
LD r,(HL)
LD r,(IX + d)
LD r,(IY + d)
LD (BC),A
LD (DE),A
LD (HL),n

LD (HL),r
LD (IX + d),n
LD (IX + d),r
LD (IY + d),n
LD (IY + d),r
LD (nn),dd
LD (nn),A
LD (nn),HL
LD (nn),IX
LD (nn),IY
LD A,(nn)
LD A,(BC)
LD A,(DE)
LD A,I
LD A,R
LD HL,(nn)
LD I,A
LD IX,nn
LD IX,(nn)
LD IY,nn
LD IY,(nn)
LD R,A
LD SP,HL
LD SP,IX

LD SP,IY
LDD
LDDR
LDI
LDIR
NEG
NOP
OR s
OTDR
OTIR
OUT (C),r
OUT (N),A
OUTD
OUTI
POP qq
POP IX
POP IY
PUSH qq
PUSH IX
PUSH IY
RES b,s
RET
RET cc
RETI

RETN
RL s
RLA
RLCA
RLC r
RLC (HL)
RLC (IX + d)
RLC (IY + d)
RLD
RR s
RRA
RRC s
RRCA
RRD
RST p
SBC A,s
SBC HL,ss
SCF
SET b,s
SLA s
SRA s
SRL s
SUB s
XOR s

Exercises

Exercise 4.1, Exercise 4.2, Exercise 4.3, Exercise 4.4, Exercise 4.5

List of Figures

Fig. 4.1: Shift and Rotate
Fig. 4.2: Eight-Bit Load Group - 'LD'
Fig. 4.3: 16-Bit Load Group - 'LD', 'PUSH' and 'POP'
Fig. 4.4: Exchanges 'EX' and 'EXX'
Fig. 4.5: Block Transfer Group
Fig. 4.6: Block Search Group
Fig. 4.7: Eight-Bit Arithmetic and Logic
Fig. 4.8: Sixteen-Bit Arithmetic and Logic
Fig. 4.9: Shift and Rotate
Fig. 4.10: Rotates and Shifts
Fig. 4.11: Nine-Bit Rotation

Fig. 4.12: Eight-Bit Rotation
Fig. 4.13: Digit Rotate Instruction (Rotate Decimal)
Fig. 4.14: Bit Manipulation Group
Fig. 4.15: General-Purpose AF Operations
Fig. 4.16: The Flags Register
Fig. 4.17: Summary of Flag Operation
Fig. 4.18: Jump Instructions
Fig. 4.19: Restart Group
Fig. 4.20: Output Group
Fig. 4.21: Input Group
Fig. 4.22: Miscellaneous CPU Control