Fig. 2.27: Intel Instruction Formats

(Reformatted for HTML.
Note references are between square brackets [ ],
and the notes themselves can be found in the main text,
in Figure 2.26.)

© Intel Corporation.
01 02 03
MNEMONIC: MOV r1,r2 MOV r,M MOV M,r
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
0 1 D D D S S S 0 1 D D D 1 1 0 0 1 1 1 0 S S S
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 (SSS) -> TMP X [3] (SSS) -> TMP
T5 TMP -> (DDD)  
M2 T1   HL OUT STATUS [6] HL OUT STATUS [7]
T2 [2] DATA -> DDD (TMP) -> DATA BUS
T3
04 05 06
MNEMONIC: SPHL MVI r,data MVI M,data
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
1 1 1 1 1 0 0 1 0 0 D D D 1 1 0 0 0 1 1 0 1 1 0
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 (HL) -> SP X X
T5  
M2 T1   PC OUT STATUS [6] PC OUT STATUS [6]
T2 [2] PC = PC + 1
B2 -> DDD		 PC = PC + 1
B2 -> TMP
T3
M3 T1   HL OUT STATUS [7]
T2 [2] (TMP) ->DATA BUS
T3
07 08 09
MNEMONIC: LXI rp,data LDA addr STA addr
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
0 0 R P 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 1 0 0 1 0
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 X X X
M2 T1 PC OUT STATUS [6] PC OUT STATUS [6] PC OUT STATUS [6]
T2 [2] PC = PC + 1
B2 -> rl		 PC = PC + 1
B2 -> Z		 PC = PC + 1
B2 -> Z
T3
M3 T1 PC OUT STATUS [6] PC OUT STATUS [6] PC OUT STATUS [6]
T2 [2] PC = PC + 1
B3 -> rh		 PC = PC + 1
B3 -> W		 PC = PC + 1
B3 -> W
T3
M4 T1   WZ OUT STATUS [6] WZ OUT STATUS [7]
T2 [2] DATA -> A (A) -> DATA BUS
T3
10 11 12
MNEMONIC: LHLD addr SHLD addr LDAX rp [4]
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
0 0 1 0 1 0 1 0 0 0 1 0 0 0 1 0 0 0 R P 1 0 1 0
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 X X X
M2 T1 PC OUT STATUS [6] PC OUT STATUS [6] rp OUT STATUS [7]
T2 [2] PC = PC + 1
B2 -> Z		 PC = PC + 1
B2 -> Z		 PC = PC + 1
DATA -> A
T3
M3 T1 PC OUT STATUS [6] PC OUT STATUS [6]  
T2 [2] PC = PC + 1
B3 -> W		 PC = PC + 1
B3 -> W
T3
M4 T1 WZ OUT STATUS [6] WZ OUT STATUS [7]
T2 [2] WZ=WZ+1
DATA -> L		 WZ=WZ+1
(L) -> DATA BUS
T3
M5 T1 WZ OUT STATUS [6] WZ OUT STATUS [7]
T2 [2] DATA -> H (H) -> DATA BUS
T3
13 14 15
MNEMONIC: STAX rp [4] XCHG ADD r
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
0 0 R P 0 0 1 0 1 1 1 0 1 0 1 1 1 0 0 0 0 S S S
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 X (HL) <--> (DE) (SSS) -> TMP
(A) -> ACT
M2 T1 rp OUT STATUS [7]   [9]
T2 [2] (A) -> DATA BUS (ACT) + (TMP) -> A
T3  
16 17 18
MNEMONIC: ADD M ADI data ADC r
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
1 0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 S S S
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 (A) -> ACT (A) -> ACT (SSS) -> TMP
(A) -> ACT
M2 T1 HL OUT STATUS [6] PC OUT STATUS [6] [9]
T2 [2] DATA -> TMP B2 -> TMP (ACT) + (TMP) + CY -> A
T3  
M3 T1 [9] [9]
T2 (ACT) + (TMP) -> A (ACT) + (TMP) -> A
19 20 21
MNEMONIC: ADC M ACI data SUB r
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
1 0 0 0 1 1 1 0 1 1 0 0 1 1 1 0 1 0 0 1 0 S S S
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 (A) -> ACT (A) -> ACT (SSS) -> TMP
(A) -> ACT
M2 T1 HL OUT STATUS [6] PC OUT STATUS [6] [9]
T2 [2] DATA -> TMP B2 -> TMP (ACT) - (TMP) -> A
T3  
M3 T1 [9] [9]
T2 (ACT) + (TMP) + CY -> A (ACT) + (TMP) + CY -> A
22 23 24
MNEMONIC: SUB M SUI data SBB r
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
1 0 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 0 0 1 1 S S S
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 (A) -> ACT (A) -> ACT (SSS) -> TMP
(A) -> ACT
M2 T1 HL OUT STATUS [6] PC OUT STATUS [6] [9]
T2 [2] DATA -> TMP B2 -> TMP (ACT) - (TMP) - CY -> A
T3  
M3 T1 [9] [9]
T2 [2] (ACT) - (TMP) -> A (ACT) - (TMP) -> A
25 26 27
MNEMONIC: SBB M SBI data INR r
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
1 0 0 1 1 1 1 0 1 1 0 1 1 1 1 0 0 0 D D D 1 0 0
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 (A) -> ACT (A) -> ACT (DDD) -> TMP
(TMP) + 1 -> ALU
T5   ALU -> DDD
M2 T1 HL OUT STATUS [6] PC OUT STATUS [6]  
T2 [2] DATA -> TMP B2 -> TMP
T3
M3 T1 [9] [9]
T2 [2] (ACT) - (TMP) - CY -> A (ACT) - (TMP) - CY -> A
28 29 30
MNEMONIC: INR M DCR r DCR M
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
0 0 1 1 0 1 0 0 0 0 D D D 1 0 1 0 0 1 1 0 1 0 1
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 X (DDD) -> TMP
(TMP) - 1 -> ALU		 X
T5   ALU -> DDD  
M2 T1 HL OUT STATUS [6]   HL OUT STATUS [6]
T2 [2] DATA -> TMP
(TMP) + 1 -> ALU		 DATA -> TMP
(TMP) - 1 -> ALU
T3
M3 T1 HL OUT STATUS [6] HL OUT STATUS [6]
T2 [2] ALU -> DATA BUS ALU -> DATA BUS
T3
31 32 33
MNEMONIC: INX rp DCX rp DAD rp [8]
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
0 0 R P 0 0 1 1 0 0 R P 1 0 1 1 0 0 R P 1 0 0 1
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 (RP) + 1 -> RP (RP) - 1 -> RP X
T5  
M2 T1   (rl) -> ACT
T2 [2] (L) -> TMP
(ACT) + (TMP) -> ALU
T3 ALU -> L,CY
M3 T1 (rh) -> ACT
T2 [2] (H) -> TMP
(ACT) + (TMP) + CY -> ALU
T3 ALU -> H,CY
34 35 36
MNEMONIC: DAA ANA r ANA M
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
0 0 1 0 0 1 1 1 1 0 1 0 0 S S S 1 0 1 0 0 1 1 0
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 DAA -> A,FLAGS [10] (SSS) -> TMP
(A) -> ACT		 (A) -> ACT
M2 T1   [9] HL OUT STATUS [6]
T2 [2] (ACT) ^ (TMP) -> A DATA -> TMP
T3  
M3 T1 [9]
T2 [2] (ACT) ^ (TMP) -> A
37 38 39
MNEMONIC: ANI data XRA r XRA M
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
1 1 1 0 0 1 1 0 1 0 1 0 1 S S S 1 0 1 0 1 1 1 0
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 (A) -> ACT (SSS) -> TMP
(A) -> ACT		 (A) -> ACT
M2 T1 PC OUT STATUS [6] [9] HL OUT STATUS [6]
T2 [2] PC = PC + 1
B2 -> TMP		 (ACT) x (TMP) -> A DATA -> TMP
T3  
M3 T1 [9] [9]
T2 [2] (ACT) ^ (TMP) -> A (ACT) x (TMP) -> A
40 41 42
MNEMONIC: XRI data ORA r ORA M
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
1 1 1 0 1 1 1 0 1 0 1 1 0 S S S 1 0 1 1 0 1 1 0
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 (A) -> ACT (SSS) -> TMP
(A) -> ACT		 (A) -> ACT
M2 T1 PC OUT STATUS [6] [9] HL OUT STATUS [6]
T2 [2] PC = PC + 1
B2 -> TMP		 (ACT) v (TMP) -> A DATA -> TMP
T3  
M3 T1 [9] [9]
T2 [2] (ACT) x (TMP) -> A (ACT) v (TMP) -> A
43 44 45
MNEMONIC: ORI data CMP r CMP M
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
1 1 1 1 0 1 1 0 1 0 1 1 1 S S S 1 0 1 1 1 1 1 0
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 (A) -> ACT (SSS) -> TMP
(A) -> ACT		 (A) -> ACT
M2 T1 PC OUT STATUS [6] [9] HL OUT STATUS [6]
T2 [2] PC = PC + 1
B2 -> TMP		 (ACT) - (TMP) -> FLAGS DATA -> TMP
T3  
M3 T1 [9] [9]
T2 [2] (ACT) v (TMP) -> A (ACT) - (TMP) -> FLAGS
46 47 48
MNEMONIC: CPI data RLC RRC
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 (A) -> ACT (A) -> ALU ROTATE<- (A) -> ALU ROTATE->
M2 T1 PC OUT STATUS [6] [9] [9]
T2 [2] PC = PC + 1
B2 -> TMP		 ALU -> A,CY ALU -> A,CY
T3  
M3 T1 [9]
T2 [2] (ACT) - (TMP) -> FLAGS
49 50 51
MNEMONIC: RAL RAR CMA
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
0 0 0 1 0 1 1 1 0 0 0 1 1 1 1 1 0 0 1 0 1 1 1 1
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 (A),CY -> ALU
ROTATE<-		 (A),CY -> ALU
ROTATE->		 (A) -> A
M2 T1 [9] [9]  
T2 [2] ALU -> A,CY ALU -> A,CY
52 53 54
MNEMONIC: CMC STC JMP addr
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
0 0 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 0 0 0 0 1 1
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 CY -> CY 1 -> CY X
M2 T1   PC OUT STATUS [6]
T2 [2] PC = PC + 1
B2 -> Z
T3
M3 T1 PC OUT STATUS [6]
T2 [2] PC = PC + 1
B3 -> W
T3
WZ OUT STATUS [11]
(WZ) + 1 -> PC
55 56 57
MNEMONIC: Jcond addr [17] CALL addr Ccond addr [17]
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
1 1 C C C 0 1 0 1 1 0 0 1 1 0 1 1 1 C C C 1 0 0
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 JUDGE CONDITION SP = SP - 1 JUDGE CONDITION
IF TRUE,
SP = SP - 1
T5
M2 T1 PC OUT STATUS [6] PC OUT STATUS [6] PC OUT STATUS [6]
T2 [2] PC = PC + 1
B2 -> Z		 PC = PC + 1
B2 -> Z		 PC = PC + 1
B2 -> Z
T3
M3 T1 PC OUT STATUS [6] PC OUT STATUS [6] PC OUT STATUS [6]
T2 [2] PC = PC + 1
B3 -> W		 PC = PC + 1
B3 -> W		 PC = PC + 1
B3 -> W
T3
M4 T1   SP OUT STATUS [16] SP OUT STATUS [16]
T2 [2] SP = SP + 1
(PCH) -> DATA BUS		 SP = SP + 1
(PCH) -> DATA BUS
T3
M5 T1 SP OUT STATUS [16] SP OUT STATUS [16]
T2 [2] SP = SP + 1
(PCL) -> DATA BUS		 SP = SP + 1
(PCL) -> DATA BUS
T3
WZ OUT STATUS [11,12] WZ OUT STATUS [11] WZ OUT STATUS [11,12]
(WZ) + 1 -> PC (WZ) + 1 -> PC (WZ) + 1 -> PC
58 59 60
MNEMONIC: RET Rcond [17] RST n
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
1 1 0 0 1 0 0 1 1 1 C C C 0 0 0 1 1 N N N 1 1 1
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR 0 -> W
INST -> TMP/IR
T4 X JUDGE CONDITION [14] SP = SP - 1
T5  
M2 T1 SP OUT STATUS [15] SP OUT STATUS [15] SP OUT STATUS [16]
T2 [2] SP = SP + 1
DATA -> W		 SP = SP + 1
DATA -> W		 SP = SP - 1
(PCH) -> DATA BUS
T3
M3 T1 SP OUT STATUS [15] SP OUT STATUS [15] SP OUT STATUS [16]
T2 [2] SP = SP + 1
DATA -> Z		 SP = SP + 1
DATA -> Z		 (TMP=00NNN000) -> Z
(PCL) -> DATA BUS
T3
WZ OUT STATUS [11] WZ OUT STATUS [11,12] WZ OUT STATUS [11]
(WZ) + 1 -> PC (WZ) + 1 -> PC (WZ) + 1 -> PC
61 62 63
MNEMONIC: PCHL PUSH rp PUSH psw
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
1 1 1 0 1 0 0 1 1 1 R P 0 1 0 1 1 1 1 1 0 1 0 1
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 (HL) -> PC SP = SP - 1 SP = SP - 1
T5
M2 T1   SP OUT STATUS [16] SP OUT STATUS [16]
T2 [2] SP = SP - 1
(rh) -> DATA BUS		 SP = SP - 1
(A) -> DATA BUS
T3
M3 T1 SP OUT STATUS [16] SP OUT STATUS [16]
T2 [2] (rl) -> DATA BUS FLAGS -> DATA BUS
T3
64 65 66
MNEMONIC: POP rp POP psw XTHL
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
1 1 R P 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 1 1
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 X X X
M2 T1 SP OUT STATUS [15] SP OUT STATUS [15] SP OUT STATUS [15]
T2 [2] SP = SP + 1
DATA -> rl		 SP = SP + 1
DATA -> FLAGS		 SP = SP + 1
DATA -> Z
T3
M3 T1 SP OUT STATUS [15] SP OUT STATUS [15] SP OUT STATUS [15]
T2 [2] DATA -> rh DATA -> A DATA -> W
T3
M4 T1   SP OUT STATUS [16]|
T2 [2] (H) -> DATA BUS
T3
M5 T1 SP OUT STATUS [16]|
T2 [2] (L) -> DATA BUS
T3
T4 (WZ) -> HL
T5
67 68 69
MNEMONIC: IN port OUT port EI
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
1 1 0 1 1 0 1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 0 1 1
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 X X SET INTE F/F
M2 T1 PC OUT STATUS [6] PC OUT STATUS [6]  
T2 [2] PC = PC + 1
B2 -> Z,W		 PC = PC + 1
B2 -> Z,W
T3
M3 T1 WZ OUT STATUS [18] WZ OUT STATUS [18]
T2 [2] DATA -> A (A) -> DATA BUS
T3
70 71 72
MNEMONIC: DI HLT NOP
OP CODE: D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0 D7D6D5D4 D3D2D1D0
1 1 1 1 0 0 1 1 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0
M1 [1] T1 PC OUT STATUS PC OUT STATUS PC OUT STATUS
T2 [2] PC = PC + 1 PC = PC + 1 PC = PC + 1
T3 INST -> TMP/IR INST -> TMP/IR INST -> TMP/IR
T4 RESET INTE F/F X X
M2 T1   PC OUT STATUS  
T2 [2] HALT MODE [20]