Programming the Z80 - Table of Contents

Introduction, System Architecture, Inside a Microprocessor, Internal Organization of the Z80, Instruction Formats, Execution of Instructions within the Z80, Hardware Summary

III. BASIC PROGRAMMING TECHNIQUES

Introduction, Arithmetic Programs, BCD Arithmetic Multiplication, Multiplication, Binary Division, Logical Operations, Instruction Summary, Subroutines, Summary

IV. THE Z80 INSTRUCTION SET

Introduction, Classes of Instructions, The Z80 Instruction Set, Summary, Individual Descriptions

V. ADDRESSING TECHNIQUES

Introduction, Possible Addressing Modes, Z80 Addressing Modes, Using the Z80 Addressing Modes, Summary

VI. INPUT/OUTPUT TECHNIQUES

Introduction, Input/Output, Parallel Word Transfer, Bit Serial Transfer, Peripheral Summary, Input/Output Scheduling, Summary

VII. INPUT/OUTPUT DEVICES

Introduction, The Standard PIO, The Internal Control Register, Programming a PIO, The Zilog Z80 PIO

VIII. APPLICATION EXAMPLES

Introduction, Clearing a Section of Memory, Polling I/O Devices, Getting Characters In, Testing A Character, Bracket Testing, Parity Generation, Code Conversion: ASCII to BCD, Convert Hex to ASCII, Finding the Largest Element of a Table, Sum of N Elements, A Checksum Computation, Count the Zeroes, Block Transfer, BCD Block Transfer, Compare Two Signed 16-bit Numbers, Bubble-Sort, Summary

IX. DATA STRUCTURES

PART 1--THEORY

Introduction, Pointers, Lists, Searching and Sorting, Section Summary

PART 2--DESIGN EXAMPLES

Introduction, Data Representation for the List, A Simple List, Alphabetic Set, Linked List, Summary

X. PROGRAM DEVELOPMENT

Introduction, Basic Programming Choices, Software Support, The Program Development Sequence, Hardware Alternatives, The Assembler, Conditional Assembly, Summary

XI. CONCLUSION

Technological Development, The Next Step

APPENDIX A

Hexadecimal Conversion Table

APPENDIX B

ASCII Conversion Table

APPENDIX C

Relative Branch Tables

APPENDIX D

Decimal to BCD Conversion

APPENDIX E

Z80 Instruction Codes

APPENDIX F

Z80 to 8080 Equivalence

APPENDIX G

8080 to Z80 Equivalence

INDEX

LIST OF FIGURES

Fig. 1.1: A Flowchart for Keeping Room Temperature Constant
Fig. 1.2: Decimal-Binary Table
Fig. 1.3: 2's Complement Table
Fig. 1.4: BCD Table
Fig. 1.5: Typical Floating-Point Representation
Fig. 1.6: ASCII Conversion Table
Fig. 1.7: Octal Symbols
Fig. 1.8: Hexadecimal Codes

Fig. 2.1: Standard Z80 System
Fig. 2.2: "Standard" Microprocessor Architecture
Fig. 2.3: Shift and Rotate
Fig. 2.4: The 16-bit Address Registers Create the Address Bus
Fig. 2.5: The Two-Stack Manipulation Instructions
Fig. 2.6: Fetching an Instruction from the Memory
Fig. 2.7: Automatic Sequencing
Fig. 2.8: Single-Bus Architecture
Fig. 2.9: Execution of an Addition - R0 into ACC
Fig. 2.10: Addition - Second Register R1 into ALU
Fig. 2.11: Result Is Generated and Goes into R0
Fig. 2.12: The Critical Race Problem
Fig. 2.13: Two Buffers Are Required (Temp Registers)
Fig. 2.14: Internal Z80 Organization
Fig. 2.15: Typical Instruction Formats
Fig. 2.16: The Code Registers
Fig. 2.17: Instruction Fetch - (PC) Is Sent to the Memory
Fig. 2.18: PC Is Incremented
Fig. 2.19: The Instruction Arrives from the Memory into IR
Fig. 2.20: Transferring C into D
Fig. 2.21: The Contents of C Are Deposited into TMP
Fig. 2.22: The Contents of TMP are Deposited into D
Fig. 2.23: Two Transfers Occur Simultaneously
Fig. 2.24: End of ADD r
Fig. 2.25: FETCH-EXECUTE Overlap during T1-T2
Fig. 2.26: Intel Abbreviations
Fig. 2.27: Intel Instruction Formats
Fig. 2.28: Transfer Contents of HL to Address Bus
Fig. 2.29: LD A,(ADDRESS) Is a 3-Word Instruction
Fig. 2.30: Before Execution of LD A
Fig. 2.31: After Execution of LD A
Fig. 2.32: Second Byte of Instruction Goes into Z
Fig. 2.33: Z80 MPU Pin out

Fig. 3.0: The Z80 Registers
Fig. 3.1: Eight-Bit Addition RES = OP1 + OP2
Fig. 3.2: LD A, (ADR1): OP1 is Loaded from Memory
Fig. 3.3: ADD A, (HL)
Fig. 3.4: LD (ADR3), A (Save Accumulator in Memory)
Fig. 3.5: 16-Bit Addition - The Operands
Fig. 3.6: Storing Operands in Reverse Order
Fig. 3.7: Pointing to the High Byte
Fig. 3.8: A 32-Bit Addition
Fig. 3.9: 16-Bit Load - LD HL,(ADR1)
Fig. 3.10: Storing BCD Digits
Fig. 3.11: Packed BCD Subtract: N1 N2-N1
Fig. 3.12: The Basic Multiplication Algorithm - Flowchart
Fig. 3.13: 8 × 8 Multiplication Program
Fig. 3.14: 8 × 8 Multiplication - The Registers
Fig. 3.15: LD BC, (MPRAD)
Fig. 3.16: LD DE, (MPDAD)
Fig. 3.17: Shift and Rotate
Fig. 3.18: Shifting from E into D
Fig. 3.19: Form for Multiplication Exercise
Fig. 3.20: Multiplication: After One Instruction
Fig. 3.21: Multiplication: After Two Instructions
Fig. 3.22: Multiplication: After Five Instructions
Fig. 3.23: One Pass Through The Loop
Fig. 3.24: Improved Multiply, Step 1
Fig. 3.25: Registers for Improved Multiply
Fig. 3.26: Improved Multiply, Step 2
Fig. 3.27: 16 × 16 Multiply - The Registers
Fig. 3.28: 16 × 16 Multiplication Program
Fig. 3.29: 16 × 16 Multiply with 32-Bit Result
Fig. 3.30: 8-Bit Binary Division Flowchart
Fig. 3.31: 16/8 Division - The Registers
Fig. 3.32: 16/8 Division Program
Fig. 3.33: Form for Division Program
Fig. 3.34: Non-Restoring Division - The Registers
Fig. 3.35: Subroutine Calls
Fig. 3.36: Nested Calls
Fig. 3.37: The Subroutine Calls
Fig. 3.38: Stack vs. Time
Fig. 3.39: Multiplication: A Complete Trace
Fig. 3.40: The Multiplication Program (Hex)
Fig. 3.41: Two Iterations Throught the Loop

Fig. 4.1: Shift and Rotate
Fig. 4.2: Eight-Bit Load Group - 'LD'
Fig. 4.3: 16-Bit Load Group - 'LD', 'PUSH' and 'POP'
Fig. 4.4: Exchanges 'EX' and 'EXX'
Fig. 4.5: Block Transfer Group
Fig. 4.6: Block Search Group
Fig. 4.7: Eight-Bit Arithmetic and Logic
Fig. 4.8: Sixteen-Bit Arithmetic and Logic
Fig. 4.9: Shift and Rotate
Fig. 4.10: Rotates and Shifts
Fig. 4.11: Nine-Bit Rotation
Fig. 4.12: Eight-Bit Rotation
Fig. 4.13: Digit Rotate Instruction (Rotate Decimal)
Fig. 4.14: Bit Manipulation Group
Fig. 4.15: General-Purpose AF Operations
Fig. 4.16: The Flags Register
Fig. 4.17: Summary of Flag Operation
Fig. 4.18: Jump Instructions
Fig. 4.19: Restart Group
Fig. 4.20: Output Group
Fig. 4.21: Input Group
Fig. 4.22: Miscellaneous CPU Control

MEDIA FILES

LIST OF EXERCISES

Exercise 2.1 (solution), Question 2.1 (answer), Question 2.2 (answer), Question 2.3 (answer).

Exercise 4.1 (solution), Exercise 4.2 (solution), Exercise 4.3 (solution), Exercise 4.4 (solution), Exercise 4.5 (solution),

Exercise 5.1 (solution), Exercise 5.2 (solution), Exercise 5.3 (solution), Exercise 5.4 (solution), Exercise 5.5 (solution), Exercise 5.6 (solution), Exercise 5.7 (solution), Exercise 5.8 (solution), Exercise 5.9 (solution), Exercise 5.10 (solution), Exercise 5.11 (solution), Exercise 5.12 (solution), Exercise 5.13 (solution).

Exercise 6.1 (solution), Exercise 6.2 (solution), Exercise 6.3 (solution), Exercise 6.4 (solution), Exercise 6.5 (solution), Exercise 6.6 (solution), Exercise 6.7 (solution), Exercise 6.8 (solution), Exercise 6.9 (solution), Exercise 6.10 (solution), Exercise 6.11 (solution), Exercise 6.12 (solution), Exercise 6.13 (solution), Exercise 6.14 (solution), Exercise 6.15 (solution), Exercise 6.16 (solution), Exercise 6.17 (solution), Exercise 6.18 (solution), Exercise 6.19 (solution), Exercise 6.20 (solution), Exercise 6.21 (solution), Exercise 6.22 (solution), Exercise 6.23 (solution), Exercise 6.24 (solution), Exercise 6.25 (solution), Exercise 6.26 (solution), Exercise 6.27 (solution), Exercise 6.28 (solution), Exercise 6.29 (solution), Exercise 6.30 (solution), Exercise 6.31 (solution), Exercise 6.32 (solution).

Exercise 8.1 (solution), Exercise 8.2 (solution), Exercise 8.3 (solution), Exercise 8.4 (solution), Exercise 8.5 (solution), Exercise 8.6 (solution), Exercise 8.7 (solution), Exercise 8.8 (solution), Exercise 8.9 (solution), Exercise 8.10 (solution), Exercise 8.11 (solution), Exercise 8.12 (solution), Exercise 8.13 (solution), Exercise 8.14 (solution), Exercise 8.15 (solution), Exercise 8.15 (solution).

TABLE OF CONTENTS

PREFACE

I. BASIC CONCEPTS

II. Z80 HARDWARE ORGANIZATION